## Getting started in structured assembly in complex SoC designs

The integration level of a system-on-chip (SoC) is defined in RTL, just like the rest of the design. Historically, RTL has been built through text editors. However, a decade or more ago, the sheer complexity of that task for the largest SoCs became unmanageable; now, most SoCs cross that threshold. Why is this? The number … Read more

## HYPERRAM 3.0 memory doubles bandwidth for low pin-count

HYPERRAM—the expansion memory for scratchpad and data buffering—has reached its third generation and is ready to serve a wide range of applications such as video buffering, factory automation, artificial intelligence (AI) edge processing, and automotive vehicle-to-everything (V2X) communications. The third generation of HYPERRAM devices from Infineon Technologies support the newly extended HyperBus interface to enable … Read more

## IC power integrity tool improves productivity

The Cadence Voltus-XFi custom electromigration and IR drop (EM-IR) software eases the design of efficient, low-power ICs. Seamlessly integrated with the company’s Quantus extraction tool, Virtuoso design environment, and Spectre simulator, Voltus-XFi can enhance productivity by as much as three times versus existing solutions. The transistor-level EM-IR tool delivers foundry-supported SPICE-level accuracy for power integrity … Read more

## DDR5 ecosystem growing with memory interface components

The DDR5 chipset solutions call for memory interface solutions that can effectively handle signal integrity and thermal management for data center servers, desktops, and laptops. Rambus claims to have answered the call by expanding its DDR5 memory interface chip portfolio with series presence detect (SPD) hub and temperature sensor devices. That complements the company’s registering … Read more

## The CHIPS Act stalemate threatens U.S. IC manufacturing revival

The roadblocks in the way of Produce Semiconductors for America Act—commonly known as the CHIPS Act—have put America’s semiconductor revival in IC manufacturing in the doldrums. Intel has pulled the plug on the groundbreaking of its Ohio fab in response to the slow passage of the CHIPS Act, while its CEO Pat Gelsinger sent a … Read more

## The 3-nm fab race: Samsung reportedly nears the finish line

Just a few days after TSMC provided details of its 3-nm process node at the company’s 2022 North America Technology Symposium, there are reports that fab archrival Samsung is starting its 3 nm-based chip manufacturing this week. TSMC plans to begin its 3 nm production by the end of this year. It’s important to note … Read more

## How EDA workloads inside the cloud reinvigorate chip design

The semiconductor industry’s journey to the cloud is now reaching the next destination: IC design companies choosing to host their EDA workloads in the cloud. Cadence’s announcement about the OnCloud SaaS and e-commerce platform powered by Amazon Web Services (AWS) is the latest reminder of a major shift in which semiconductor design is steadily moving … Read more

## Pitfalls of mixing formal and simulation: How to stay out of trouble

Driven by the need to objectively measure the progress of their verification efforts and the contributions of different verification techniques, IC designers have adopted coverage as a metric. However, what exactly is being measured is different depending on the underlying verification technology in use. In Part 1, we outlined the textbook definitions of simulation and … Read more